This application claims priority to Korean Patent Application No. 2001-14112, filed on Mar. 19, 2001, which is commonly owned and incorporated by reference herein.
1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of minimizing skew between plural-bit output data and a method thereof.
2. Description of Related Art
Semiconductor devices that output data comprising a large number of bits typically output the data bits simultaneously (i.e., in parallel). When the logic levels of the plural-bit output data simultaneously transition, a large amount of electrical current is applied to a power line, which causes a transition noise due to parasitic components of the power line. As a result, output data can be delayed and distorted.
Further, if a portion of the output data transits in one direction to a logic state (e.g., from a logic xe2x80x9chighxe2x80x9d to a logic xe2x80x9clowxe2x80x9d level), and another portion of the output data transits in the opposite direction (e.g., from a logic xe2x80x9clowxe2x80x9d to a logic xe2x80x9chighxe2x80x9d level), a delay time difference occurs between the output data because of the difference of the transition directions. As a result, skew occurs between the output data. The skew will increase as the number of bits comprising the output data increases, the parasitic components increase, and as the operation speed increases.
FIG. 1 is a circuit diagram illustrating a conventional data output circuit. The data output circuit comprises a plurality of data output drivers 10-1 to 10-n, parasitic components 12 and 14, and a capacitor C3. The data output drivers 10-1 to 10-n drive input data bits D1 to Dn to generate output data bits DQ1 to DQn, respectively. Each of the data output drivers 10-1 to 10-n comprises an inverter comprising a PMOS transistor P1 and an NMOS transistor N1. The parasitic component 12 is represented by a resistor R1, an inductor L1, and a capacitor C1, connected between an external power voltage VDDQ and each power voltage terminal of the data output drivers 10-1 to 10-n. The parasitic component 14 is represented by a resistor R2, an inductor L2 and a capacitor C2, connected between an external ground voltage VSSQ and each ground voltage terminal of the data output drivers 10-1 to 10-n. 
The data output drivers 10-1 to 10-n drive the input data bits D1 to Dn to generate the output data bits DQ1 to DQn, respectively. When the output data bits DQ1 to DQn change their logic levels (e.g., from a high level to a low level or vice versa), a large amount of current is drawn through power lines for receiving the external power voltage VDDQ and for receiving the external ground voltage VSSQ. Consequently, a transition noise occurs due to the parasitic components 12 and 14. The capacitor C3 is connected between the parasitic components 12 and 14 for interactively changing the external power voltage VDDQ and the external ground voltage.
FIGS. 2A to 2C are graphs illustrating a relationship between the external power voltage VDDQ the external ground voltage VSSQ, and the output data bits DQ1 to DQn of FIG. 1, during logic level transitions of output data bits DQ1 to DQn.
As illustrated in FIG. 2A, when input data bits D1 to D((n+2) transition from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level and input data bits D((n+1)/2) to Dn transition from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level, output data bits DQ1 to DQ(n/2) transition from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level and output data bits DQ((n+1)/2) to DQn transition from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level. Because of the transition of each of the n/2 bits, the level of the external power voltage VDDQ falls and a level of the external ground voltage VSSQ rises.
As further illustrated in FIG. 2B, when input data bits D1 to D(nxe2x88x921) transition from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level and input data bit Dn transitions from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level, output data bits DQ1 to DQ(nxe2x88x921) transition from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level and output data bit DQn transitions from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level.
At this moment, because the input data bits D1 to D(nxe2x88x921) transition from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level, the voltage levels of the external ground voltage VSSQ and the external power voltage VDDQ rise significantly due to the capacitor C3. Consequently, a threshold voltage of each NMOS transistor N1 of the data output drivers 10-1 to 10-n rises, causing the transition time from a logic xe2x80x9chighxe2x80x9d to a logic xe2x80x9clowxe2x80x9d level of the output data bits DQ1 to DQ(nxe2x88x921) to become slower as shown in FIG. 2B. Further, a threshold voltage of each PMOS transistor P1 of the data output drivers 10-1 to 10-n also rises, so that the transition time from a logic xe2x80x9clowxe2x80x9d to a logic xe2x80x9chighxe2x80x9d level of the output data bit DQn becomes faster. That is, skew occurs between output data bits DQ1 to DQ(nxe2x88x921) and the output data bit DQn, as illustrated in FIG. 2B.
Further, as shown in FIG. 2C, when the transition time from a logic xe2x80x9clowxe2x80x9d to a logic xe2x80x9chighxe2x80x9d level of the output data bits DQ1 to DQ(nxe2x88x921) becomes slower, and the transition time from a logic xe2x80x9chighxe2x80x9d to a logic xe2x80x9clowxe2x80x9d level of the output data bit DQn becomes faster, skew occurs between the output data bits DQ1 to DQ(nxe2x88x921) and the output data bit DQn.
As described above, in conventional semiconductor devices, as the number of output bits increases, skew occurs between output data that transitions from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level and other output data that transitions from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level.
To overcome the above problems, it is an object of the present invention to provide a semiconductor device and output method thereof for minimizing skew between plural-bit output data.
According to one aspect of the present invention, a data output circuit of a semiconductor device comprises a plurality of data output drivers for generating plural-bit output data. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state, in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state, in response to signals received from other data output drivers.
Preferably, the first delay circuit comprises a plurality of first switching devices, which are activated in response to the first state of the input data, for transitioning a level of the input data from the first state to the second state; and a plurality of first capacitors for delaying the transition delay time of the input data having the first state. Each of first capacitors are connected to a corresponding one of the first switching devices and an internal ground voltage. The second delay circuit preferably comprises a plurality of second switching devices, which are activated in response to the second state of the input data, for transitioning a level of the input data from the second state to the first state; and a plurality of second capacitors, connected between the plurality of the second switching devices and an internal ground voltage, for varying the transition delay time of the input data having the second state.
According to another aspect of the present invention, a semiconductor device comprises a controller for receiving plural-bit input data and a plurality of data output drivers. The plural-bit input data comprise a first group of bits that transition from a first state to a second state and a second group of bits that transition from the second state to the first state. The controller compares the number of bits in the first group and the number of bits in the second group to generate a falling transition delay time control signal and a rising transition delay time control signal. The plurality of data output drivers generate plural-bit output data in response to the plural-bit input data and the falling and rising transition delay time control signals.
According to another aspect of the present invention, a semiconductor device comprises a controller for receiving plural-bit input data, wherein the plural-bit input data comprises a first group of bits that transition from a first state to a second state and a second group of bits that transition from the second state to the first state, and wherein the controller compares the number of bits in the first group and the number of bits in the second group to generate a falling transition delay time control signal and a rising transition delay time control signal; a plurality of clock signal generators for receiving a clock signal and generating a delayed clock signal with respect to each of the plural-bit input data in response to the rising transition delay time control signal and the falling transition delay time control signal, respectively; a plurality of registers for receiving the plural-bit input data in response to the corresponding delayed clock signal, respectively; and a plurality of data output drivers for generating plural-bit output data in response to the output from the plurality of the registers, respectively.
According to further aspect of the present invention, a method is provided for outputting plural-bit output data in a semiconductor device comprising a plurality of data output drivers, in which the plurality of data output drivers are connected between an external power voltage and an external ground voltage, pull up the plural-bit output data is in response to plural-bit input data of a first state, and pull down the plural-bit output data in response to the plural-bit input data of a second state. The method comprises the steps of: receiving a first group of the plural-bit input data that transition from the second state to the first state and a second group of the plural-bit input data that transition from the first state to the second state; comparing the number of bits in the first group with the number of bits in the second group to generate a rising transition delay time control signal and a falling transition delay time control signal; controlling transition delay time of the first group and the second group in response to the rising transition delay time control signal and the falling transition delay time control signal, respectively; and generating the plural-bit output data in response to the plural-bit input data.